It is known that integrated circuits can be damaged by transient over-voltage conditions which can stress transistors which have, for example, been designed with a given breakdown voltage, for example because the majority of the transistors have been formed using a “standard” fabrication process offered by a fabricator (and often defined by voltage) where the majority of the transistors have a standard dimension to give a desired trade-off between speed, packing density and voltage handling. To address this risk of over-voltage damage or damage from electrostatic discharge (ESD), it is known that protection circuits can be provided. In early integrated circuits these protection devices were often implemented as diodes between a pin and a supply rail. However these protection circuits are crude and cannot be used in circuits such as line drivers or bus drivers where being able to withstand a voltage in excess of the supply rails of a device without opening an uncontrolled current path is a system requirement.
In general the integrated circuit manufacturer selects the transistor size/fabrication process based on the design requirements of the functional circuit rather than prioritizing the requirements of any embedded over-voltage protection system. This makes sense as transistors able to withstand high voltages and currents which might occur in an over-voltage event tend to be physically big which reduces their speed due to the combined effect of parasitic capacitance and carrier transit time. Also such devices consume more area on a wafer, so ultimately high voltage and high current handling gives rise to more expensive and slower transistors.
More recently ESD or other over-voltage event protection circuits have been implemented using transistors within an integrated circuit. However, the transistor parameters and fabrication processes used in these integrated over-voltage protection circuits have not typically been optimized for their over-voltage function. Instead, the performance characteristics of these over-voltage transistors have largely been dependent upon fabrication parameters chosen to optimize other transistors that carry out the primary function of the circuit to be protected. Therefore, it has mainly been a matter of luck whether the fabrication parameters chosen to optimize majority devices are suitable for use in the accompanying over-voltage protection circuit. While it is possible to separately optimize an over-voltage protection circuit using additional processing steps, those additional processing steps carry increased costs. A typical over-voltage event is an electrostatic discharge (ESD) event.
Additionally devices may have to withstand “surge” events. These also manifest themselves as over-voltage events but can be quite different to ESD events. An ESD event can be generalized as being an event of very short duration, with a very large excess voltage but little energy. Such an event may occur as a result of a person becoming electrostatically charged when walking over a nylon carpet. A surge event is slower (for example it may result from an inductive load being switched) and typically has a much lower peak voltage but may involve a large amount of energy.